Call for Participation: FPGA for HPC Workshop 2021 (virtual workshop)


筑波大学の小林 諒平です.

本MLをお借りして,2021年9月7日 (木) 06:00 – 10:40 PDT (22:00 – 02:40 JST) にオンライン開催の IEEE Cluster 2021併設ワークショップ FPGA for HPC Workshop 2021 (HPC FPGA 2021) の参加登録の案内をさせていただきます.是非ご参加頂ければ幸いです.

Early Registration が ** 日本時間で 8/28 (土) 15:59 まで ** ですので,参加希望される方はこちら ( から登録をお済ませください.

FPGA for HPC Workshop 2021
held in conjunction with IEEE Cluster 2021

Tuesday, September 7th, 2021


All attendees must register at the IEEE Cluster website (
Registrants will be given the link for attendance nearer to the workshop date.

Early registration deadline: August 27, 2021 (11:59pm Pacific)

Early registration
– IEEE Member $100
– IEEE Life Member $55
– IEEE Student Member $70
– Non-member $120
– Student Non-member $85

Standard registration
– IEEE Member $115
– IEEE Life Member $65
– IEEE Student Member $85
– Non-member $140
– Student Non-member $105

Objective of Workshop:

The cluster computing for High Performance Computing (HPC) has been improved both its performance and data handling capabilities mainly thanks to the increase of operation frequency, number of cores per chip and degree of parallelism per instruction. Facing to the limit of power consumption, however, recent world top-class clusters are equipped with Graphics Processing Unit (GPU) to enhance their performance/power efficiency for many applications suitable with this accelerating architecture. On the other hand, Field Programmable Gate Array (FPGA) has been attractive to compensate several performance difficulties in GPU-only acceleration such as (partial) lack of parallelism in the application, its passive operation under CPU control, not ready for direct communication by itself, etc. We focus on recent great advantage of high-end FPGAs to cover these problems by GPU-only solution as the new technology for next generation of accelerated computing.

FPGA for HPC 2021 Workshop targets the FPGA technologies for mainly (but not limited) High Performance Computing to support computation power, high bandwidth memory usage, optimized FPGA design, programming technique, high speed communication link utilization, etc. The workshop is constructed with contributed technical paper presentation, keynote and invited talks and short panel discussion. The organizers like to provide this workshop as a cross field for exchanging valuable knowledge and technology to be shared by researchers on advanced FPGA technology and applications.

Keynote Speaker:

Kentaro Sano
Team Leader, Processor Research Team, Center for Computational Science, RIKEN

Challenges for Reconfigurable HPC with FPGA Cluster “ESSPER” Connected to Supercomputer Fugaku

Workshop’s Program:
Time Zone Starting – Ending
PDT (US Pacific) 06:00 – 10:40
EDT (US East Coast) 09:00 – 13:40
CEST (Central Europe) 15:00 – 19:40
CST (China) 21:00 – 01:40
JST (Japan, Korea) 22:00 – 02:40

Time zone is PDT.

06:00 am (PDT) Welcome Message, Taisuke Boku (Center for Computational Sciences, University of Tsukuba)
06:10 am Keynote Talk, Kentaro Sano (RIKEN Center for Computational Sciences)
06:55 am Accelerating advection for atmospheric modelling on Xilinx and Intel FPGAs, Nick Brown (The University of Edinburgh)
07:25 am HBM2 Memory System for HPC Applications on an FPGA, Norihisa Fujita (Center for Computational Sciences, University of Tsukuba)
07:45 am A memory bandwidth improvement with memory space partitioning for single-precision floating-point FFT on Stratix 10 FPGA, Takaaki Miyajima (Meiji University)
08:05 am Break
08:25 am From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics, Karl F. A. Friebel (Technische Universitaet Dresden)
08:55 am An FPGA-based storage control with load balancing, Yoshiki Yamaguchi (University of Tsukuba)
09:15 am Optimisation of an FPGA Credit Default Swap engine by embracing dataflow techniques, Nick Brown (The University of Edinburgh)
09:35 am TIGRA: A Tightly Integrated GenericRISC-V Accelerator Interface, Brad Green (Clemson University)
09:55 am Panel Discussion: “FPGA-cluster deployment and adoption to application users”, Speaker is TBD
10:40 am Closing Remarks, Speaker is TBD

Workshop Coverage Area:

The workshop covers the following, but not limited, FPGA related research on system and application for High Performance Computing and other useful applications.

– FPGA-ready cluster system hardware and software, including FPGA itself, supporting system on host CPU, etc.
– FPGA programming model and supporting system
– FPGA applications including HPC, AI, data science, etc.
– FPGA optical link communication system
– Parallel FPGA programming system
– Peripheral controlling by/with FPGA including network, storage, etc.
– Multi-hybrid system with FPGA and other accelerators


All accepted papers are published in the workshop volume of IEEE Cluster 2021.


Organizing Committee
Chair: Taisuke Boku, Unviersity of Tsukuba (Chair)
– Martin Herbordt, Boston University
– Franck Cappello, Argonne National Laboratory
– Kentaro Sano, RIKEN R-CCS

Organizing Deputy Co-Chairs
– Ryohei Kobayashi, University of Tsukuba
– Norihisa Fujita, University of Tsukuba

Program Committee
Chair: Martin Herbordt, Boston University
– Taisuke Boku, University of Tsukuba
– Franck Cappello, Argonne National Laboratory
– Paul Chow, University of Toronto
– David Donofrio, Lawrence Berkeley National Laboratory
– Norhisa Fujita, University of Tsukuba
– Tong Geng, Pacific Northwest National Lab
– Diana Goehringer, Technische Universität Dresden
– Ryohei Kobayashi, University of Tsukuba
– Venkata Krishnan, Intel
– Seyong Lee, Oak Ridge National Laboratory
– Xavier Martorell, Barcelona Supercomputing Center
– Hiroki Matsutani, Keio University
– Hiroki Nakahara, Tokyo Institute of Technology
– Yasunori Osana, University of Ryukyus
– Christian Plessl, Paderborn University
– Kentaro Sano, RIKEN R-CCS
– Yoshiki Yamaguchi, University of Tsukuba
– Kazutomo Yoshii, Argonne National Laboratory


Any question on the workshop should be mailed to

University of Tsukuba
Center for Computational Sciences
E-mail: kobayashi at