Call for papers: FPGA for HPC Workshop 2021 (virtual workshop)


筑波大学の小林 諒平と申します.

本MLをお借りして,IEEE Cluster 2021 の併設ワークショップ FPGA for HPC Workshop 2021 (HPC FPGA 2021) の Call for Papers のご案内をさせて戴きます.


FPGA for HPC Workshop 2021
held in conjunction with IEEE Cluster 2021

Tuesday, September 7th, 2021

Conference Operation:

IEEE Cluster 2021 and its workshops will no longer take place in Portland, Oregon, USA and will instead be operated virtually.

Objective of Workshop:

The cluster computing for High Performance Computing (HPC) has been improved both its performance and data handling capabilities mainly thanks to the increase of operation frequency, number of cores per chip and degree of parallelism per instruction. Facing to the limit of power consumption, however, recent world top-class clusters are equipped with Graphics Processing Unit (GPU) to enhance their performance/power efficiency for many applications suitable with this accelerating architecture. On the other hand, Field Programmable Gate Array (FPGA) has been attractive to compensate several performance difficulties in GPU-only acceleration such as (partial) lack of parallelism in the application, its passive operation under CPU control, not ready for direct communication by itself, etc. We focus on recent great advantage of high-end FPGAs to cover these problems by GPU-only solution as the new technology for next generation of accelerated computing.

FPGA for HPC 2021 Workshop targets the FPGA technologies for mainly (but not limited) High Performance Computing to support computation power, high bandwidth memory usage, optimized FPGA design, programming technique, high speed communication link utilization, etc. The workshop is constructed with contributed technical paper presentation, keynote and invited talks and short panel discussion. The organizers like to provide this workshop as a cross field for exchanging valuable knowledge and technology to be shared by researchers on advanced FPGA technology and applications.

Important Dates:

– Paper submission deadline: June 25th
– Acceptance notification: July 19th
– Final camera ready deadline: July 30th

Workshop Coverage Area:

The workshop covers the following, but not limited, FPGA related research on system and application for High Performance Computing and other useful applications.

– FPGA-ready cluster system hardware and software, including FPGA itself, supporting system on host CPU, etc.
– FPGA programming model and supporting system
– FPGA applications including HPC, AI, data science, etc.
– FPGA optical link communication system
– Parallel FPGA programming system
– Peripheral controlling by/with FPGA including network, storage, etc.
– Multi-hybrid system with FPGA and other accelerators


All accepted papers are published in the workshop volume of IEEE Cluster 2021.

Paper Submission:

All contributed papers should be submitted through EasyChair titled “HPC-FPGA-Cluster2021”.

– Submissions must be in PDF format and must conform to the following IEEE Xplore layout, page limit, and font size.
– Submissions are required to be no more than 8 pages INCLUDING text, figure, table and reference list.
– Submissions must be single-spaced, 2-column numbered pages in IEEE Xplore format (8.5×11-inch paper, margins in inches – top: 0.75, bottom: 1.0, sides:0.625, and between columns:0.25, main text: 10pt).
– Papers will be reviewed SINGLE-BLIND. Author names and affiliations should be included in the submitted paper, and appropriate citations of prior work must be included.
– Only web-based submissions are allowed.

More details:


Organizing Committee
Chair: Taisuke Boku, Unviersity of Tsukuba (Chair)
– Martin Herbordt, Boston University
– Franck Cappello, Argonne National Laboratory
– Kentaro Sano, RIKEN R-CCS

Organizing Deputy Co-Chairs
– Ryohei Kobayashi, University of Tsukuba
– Norihisa Fujita, University of Tsukuba

Program Committee
Chair: Martin Herbordt, Boston University
– Taisuke Boku, University of Tsukuba
– Franck Cappello, Argonne National Laboratory
– Paul Chow, University of Toronto
– Norhisa Fujita, University of Tsukuba
– Tong Geng, Pacific Northwest National Lab
– Diana Goehringer, Technische Universität Dresden
– Ryohei Kobayashi, University of Tsukuba
– Venkata Krishnan, Intel
– Seyong Lee, Oak Ridge National Laboratory
– Xavier Martorell, Barcelona Supercomputing Center
– Hiroki Matsutani, Keio University
– Hiroki Nakahara, Tokyo Institute of Technology
– Yasunori Osana, University of Ryukyus
– Christian Plessl, Paderborn University
– Kentaro Sano, RIKEN R-CCS
– Yoshiki Yamaguchi, University of Tsukuba
– Kazutomo Yoshii, Argonne National Laboratory


Any question on the workshop should be mailed to